Intel announced by 3D three gate transistor design,KM732V596A Suppliers, the minimum line width of22 nm Ivy Bridge microprocessor production successful, and in April 29th the global sales.
According to published data, the series CPU has1400000000 transistors, chip area is only 25mm x 25mm, we used 3D three gate transistor technology, so that the chip in the lower voltage operation, and further reduce the transistor leakage current, and prior to the32 nm2D transistor CPU compared with, in the low voltage working mode switching speed is improved by 37%, reduces the power consumption of50%, compared with the22planar transistors similar CPU power consumption has been reduced by 19%.
This is indeed a new span of technical progress, indicates that Intel company is indeed the world leader in semiconductor manufacturing technology. Since May 4, 2011, Intel company announces formally will use the3D three gate transistor design technology for Ivy Bridge microprocessor production since the plan, to the Ivy Bridge microprocessor product formal batch appears on the market, after nearly a year of time.
Why”3D” plus “three gate transistor ( Tri-Gate )” this one appellation? This is the key to technology improvement. In contrast to previous planar transistor model structure mode, this change is mainly reflected in the only in the bottom region of the”1″ flat” gate”, developed into a three-dimensional structure of”3″ shape” gate”, control current at the same time from the shape of a cube3surface grid ( the sides and top of ) the source and drain of the transistor on-off current control, so it is called” the three transistor gate”. The” three gates” structure is shaped like a book, the original is ” lay flat placed”, now” stand placed”. With previous flat”1 faces” gate transistor, which saves chip area, also reduced the transistor leakage current, improves the switching speed. To improve the CPU performance, lower power consumption, raise per unit area integration.
3D technology public opinions are divergent.
Intel: Fabless mode or to go into a cul-de-sac
April 26th Intel process technology department director Mark Bohr at the Ivy Bridge processor conference pointed out, Fabless ( fabless semiconductor business model has faster ) to go into a cul-de-sac. He thinks, TSMC recently announced it will only provide a20 nm process, is a recognition of the failing that, obviously they cannot in the next mainstream process node is provided such as a 3D transistor to reduce leakage current technology. At the same time, high cannot use TSM22 nm process technology, wafer foundry pattern is crumbling.
According to Bohr, the Ivy Bridge processor is able to successfully, it is one of the secrets from the process technology and chip designers of the close relationship between the mode of IDM, and this only in factories can be realized. Intel PC client group, the new general manager of Kirk Skaugen, Bohr and Ivy Bridge processor is responsible for the project manager Brad Heaney presided over the session together made the above remarks. ” IDM pattern of manufacturing products, indeed help us to solve the production Ivy Bridge such a small size, complex components of the problems encountered.”
According to the report, at present, the industry also has many people hold such views. EETimes the United States edition has many articles on IC design industry and technology providers, need to have closer cooperation. One from the Nvidia entity design department recently in the Mentor Graphics ‘s annual meeting, also emphasized the same arguments.
TSM:3D architecture in the14 nm before is not necessary
According to reports, TSMC and GlobalFoundries ‘s director of research, offerred very convincing data development example, proved 3D transistor architecture at 14 nm process node before is not necessary. Said TSMC,20 nm node has not enough room to create high performance process and low power consumption process between the apparent change.
For TSMC’s20 nm process planning, high comment on. But high in the recent quarterly financial statement said, the company could not be TSMC enough28 nm process capacity to respond to their needs, is currently seeking a new foundry sources, and is expected to be later this year formally28 nm manufacturing process entrusted to place an order.
ARM:3D transistor will not change industry structure
ARM Wu Xiongang, Intel3D transistor will not change industry structure. Wu Xiongang said, FinFet /3D transistor technology development to the industry enterprises, the innovation is not unique to the intel. The industry will be in the next generation of products gradually adopted the technology, then the technology will be used in SoC design. So the Intel3D transistor does not give consumer electronics or mobile product market competition brings change. The ARM ecosystem in the22 nm node is very active, and has already begun to join the20 nm, whereas ARM is also active in the development of the IP node.
In the consumer electronics and mobile products, the use of a server and desktop computer late generation technology is not a new thing. But in the consumer electronics and mobile products, as a result of its market scale and product price factor, a cost, performance and power consumption of the optimal combination is very important, factory production capacity is also very important.
3D technology in the early generations of product design and manufacturing needs to work more closely together, improve the design process. Therefore, not suitable for a highly integrated mobile system on chip design, and the system design is currently promoting a wide range of semiconductor industry innovation.
Wu Xiongang points out, Intel this technology with them in the process of innovation are consistent. While ARM’s innovation comes from the ecological system, covering technology, micro architecture and system on chip ( SoC ) design and other aspects.
IBM: seeking material to solve the problem of heat dissipation
IBM is secure under a more mature technology for 3D IC products of mass production, the use of3D technology is low density silicon through hole technology. According to reports, the technology is currently the main problem is the heat problem, is expected before the end of 2012 to solve these problems.
According to another report, IBM and 3M company cooperation, seek a kind of materials to solve the3D IC production in the face of the radiating problem. 3M’s mission is to create a suitable stacked die for use between the underfill material, this is a kind of electrical insulating materials ( like dielectric), thermal conductivity than silicon ( as metal ). ” Now we are doing the experiment, by 2013 hope began extensive commercial.” 3M company electronic market materials division technical director Chen Ming said.
” Have proficiency in a particular line of time has passed.” IBM research vice president Bernard Meyerson said, if only depending on the material or the chip architecture or network architecture or software and integrated, might not be able to win the competition for 3D. If we want to win the war, need to use all the resources.
3D chip stack is not the latest technology
It is reported, at present the most advanced technology should be used silicon through-hole3D chips are stacked, almost leading semiconductor companies are working on the technology.
Last year’s International Solid-State Circuits Conference, Samsung announced its 2.5D technology, the2.5D technology is very suitable for allegedly located in system level chip with silicon through holes and convex blocks stacked DRAM bare chip. Samsung prepared to this technique is used in1Gbit mobile DRAM products, and plans in 2013makes the mobile DRAM capacity increased to 4Gbit.
Xilinx company launched a2.5D encapsulation technology of FPGA solutions, this technology can be in silicon intermediary layer interconnects the 4side by side with convex block of the Virtex-7FPGA. At present, TSMC also is producing the silicon intermediary layer, using the silicon through-hole technology redistribution of FPGA interconnect, TSMC has pledged in 2013 to its OEM customers such conversion technology.
And there are a number of companies are currently in the3D IC production technology research and development. Tezzaron Semiconductor company for its tungsten silicon through-hole technology provides the 3D IC design services have for many years. Tezzaron FaStack process from thin to 12micron wafer heterogeneous die manufacturing 3D chip. This process has the stacked DRAM wide I / O characteristics, the deep-submicron interconnect density amounts to every square millimeter of1000000 silicon through hole.
3D technology can give chip design brings lots of new ideas. The designer must use a different way of thinking, to the innovative way to combine CPU, memory and I / O function, this is everything only in a postage stamp sized area placed side by side can not do.
According to relevant data, the production of 3D IC technology is not a new technology, stacked chip idea itself can be traced back to the 1958issued to the transistor pioneer William Shockley company early patent. Since then, the industry has used many stacked die configuration scheme. For example, the MEMS sensor stacked on top of ASIC, or small DRAM stack in the processor core.
Last year EE Times ACE annual innovation awards Zvi Or-Bach think3D IC designers need from the silicon through-hole technology transition to super high density monolithic 3D technology. BeSang Inc claims being made without silicon monolithic3D memory chip prototype, and is expected to debut in2012.
According to the report, at present there are many semiconductor association in a research setting3D technical standards. Semiconductor equipment and Materials International Organization ( SEMI ) of 4 teams in 3D IC standard. The three-dimensional stacked IC standard committee members including SEMI Globalfoundries, IBM Intel, HP, Samsung and United Microelectronics Corp ( UMC ) and Amkor, ASE, European Interuniversity Microelectronics Center ( IMEC ), Asian Industrial Technology Research Institute ( ITRI ), Olympus, Qualcomm, Semilab, Tokyo electron and Xilinx company. Read the rest of this entry »